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PIC18FXX39

DS30485A-page 24

Preliminary

2002 Microchip Technology Inc.

3.1

Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected. To take advantage of the POR cir-

cuitry, just tie the MCLR pin directly (or through a resis-

tor) to VDD. This will eliminate external RC components

usually needed to create a Power-on Reset delay. A

minimum

rise

rate

for

VDD

specified

(parameter D004). For a slow rise time, see Figure 3-2.

When the device starts normal operation (i.e., exits the

RESET condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in RESET until the operating

conditions are met.

FIGURE 3-2:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

3.2

Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out

(parameter 33) only on power-up from the POR. The

Power-up Timer operates on an internal RC oscillator.

The chip is kept in RESET as long as the PWRT is

active. The PWRT’s time delay allows VDD to rise to an

acceptable level. A configuration bit is provided to

enable/disable the PWRT.

The power-up time delay will vary from chip-to-chip due

to VDD, temperature and process variation. See DC

parameter D033 for details.

3.3

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over (parameter 32). This ensures that

the crystal oscillator or resonator has started and

stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

3.4

PLL Lock Time-out

With the PLL enabled, the time-out sequence following

a Power-on Reset is different from other Oscillator

modes. A portion of the Power-up Timer is used to pro-

vide a fixed time-out that is sufficient for the PLL to lock

to the main oscillator frequency. This PLL lock time-out

(TPLL) is typically 2 ms and follows the Oscillator

Start-up Time-out (OST).

3.5

Brown-out Reset (BOR)

A configuration bit, BOREN, can disable (if clear/

programmed), or enable (if set) the Brown-out Reset

circuitry. If VDD falls below parameter D005 for greater

than parameter 35, the brown-out situation will reset

the chip. A RESET may not occur if VDD falls below

parameter D005 for less than parameter 35. The chip

will remain in Brown-out Reset until VDD rises above

BVDD. If the Power-up Timer is enabled, it will be

invoked after VDD rises above BVDD; it then will keep

the chip in RESET for an additional time delay

(parameter 33). If VDD drops below BVDD while the

Power-up Timer is running, the chip will go back into a

Brown-out Reset and the Power-up Timer will be initial-

ized. Once VDD rises above BVDD, the Power-up Timer

will execute the additional time delay.

3.6

Time-out Sequence

On power-up, the time-out sequence is as follows:

First, PWRT time-out is invoked after the POR time

delay has expired. Then, OST is activated. The total

time-out will vary based on oscillator configuration and

the status of the PWRT. For example, in RC mode with

the PWRT disabled, there will be no time-out at all.

Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and

Figure 3-7 depict time-out sequences on power-up.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire.

Bringing MCLR high will begin execution immediately

(Figure 3-5). This is useful for testing purposes or to

synchronize more than one PIC18FXXX device

operating in parallel.

Table 3-2 shows the RESET conditions for some

Special Function Registers, while Table 3-3 shows the

RESET conditions for all the registers.

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 k

is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

3: R1 = 100

to 1 k will limit any current flow-

ing into MCLR from external capacitor C, in

the event of MCLR/VPP pin breakdown due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS).

VDD

MCLR

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